The reading-in of the input signals by the industrial process and the outputting of the output signals to the industrial process are performed in an interface module by means of the processing unit comprised therein within a so-called cycle time. This cycle time is normally very different from the time between two access periods of the higher-level unit to the relevant interface module. The input and output signals can, therefore, not be forwarded or processed immediately, but have to be temporarily stored in the interface module. A buffer circuit for this is known from the EP 0 843 843 B1 with which a processing unit of the interface module described therein on the one hand and a bus connection on the other in a buffer memory reserve one of three memory areas (buffers), so that it is guaranteed at all times that the processing unit and bus connection have access to a buffer in the buffer memory into which new data can be written without overwriting data written immediately prior thereto. However, it has been found that there is a requirement to improve the flexibility of a fixed relationship of two buffers in each case with the two communication entities, that is the processing unit on the one hand and the bus connection on the other, associated with the approach in the aforementioned EP 0 843 843 B1.